Abstract :

This study use 32nm FinFET technology to develop and analyze a CMOS full adder, aiming to overcome the limitations of traditional bulk CMOS at deep submicron nodes. FinFETs have been the best choice for low-power, high-performance digital circuits because they better regulate short-channel effects and have fewer leakage currents. We use FinFETs in both static and dynamic logic styles to design the entire adder, which is a core part of arithmetic and logic circuits. We then test its performance measures, such as power consumption, latency, and power-delay product (PDP). The proposed architecture leverages the benefits of FinFETs' double-gate topology to achieve an optimal balance between speed and power efficiency. We used industry-standard tools to do comparative simulations to see how well the FinFET-based complete adder worked compared to its bulk CMOS counterpart. The results demonstrate big improvements in energy economy, switching speed, and overall scalability. This means that th