Abstract :

Growing complexity in the design of today's digital systems necessitates the creation of electronic system-level (ESL) approaches that include automation and optimization at a higher level of abstraction. ESL design frameworks heavily depend on the specifics of the application's concept of concurrency. When it comes to describing task-level concurrent behaviour in the hardware synthesis design cycle, state-of-the-art concurrent specification models fall short. We present a task-level data model (TLDM) for hardware synthesis of data-processing applications, based on the concurrent collection (CnC) paradigm, which allows for maximal task rescheduling flexibility. In order to represent task instances, array accesses, and dependencies succinctly, TLDM incorporates polyhedral models. We demonstrate the benefits of our TLDM definition over other popular concurrency specifications using examples.