Abstract :

This paper presents the comprehensive design, simulation, and verification of a custom RISC-V processor architecture utilizing RTL implementation in SystemVerilog. The processor is based on the RV32I instruction set architecture and employs a 5-stage pipelined design comprising instruction fetch, instruction decode, execution, memory access, and write back stages. A hazard control unit with stall management is integrated to handle data and control hazards effectively. The design follows a Harvard architecture, ensuring separate storage for instructions and data to enhance throughput. Simulation and verification are performed using advanced functional and temporal verification techniques in System-Verilog. The results validate that RTL-based pipelining combined with System-Verilog verification provides an effective methodology for high-speed, low-power RISC processor designs.